NXP Semiconductors /LPC43xx /PMC /PD0_SLEEP0_HW_ENA

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Interpret as PD0_SLEEP0_HW_ENA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENA_EVENT0)ENA_EVENT0 0 (ENA_EVENT1)ENA_EVENT1 0RESERVED

Description

Hardware sleep event enable register

Fields

ENA_EVENT0

Writing a 1 enables the Cortex-M4 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register.

ENA_EVENT1

Writing a 1 enables the Cortex-M0 core and the Cortex-M0 subsystem core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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